The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device.
As a semiconductor power element, a junction FET (Field Effect Transistor) has been developed in which a pn junction is formed between a channel forming layer and a gate layer and the width of a depletion layer extending from the pn junction is controlled to thereby turn on or off a channel. For example, Japanese Unexamined Patent Application Publication No. 2010-147405 discloses a vertical type junction FET using silicon carbide for a substrate and an epitaxial layer, in which an impurity concentration in a part of a channel forming layer that forms a pn junction with a gate layer is set to be higher than the impurity concentration in a central part of the channel forming layer and the epitaxial layer, thereby achieving both an improvement in source-drain breakdown voltage and a reduction in on-resistance.